This application claims the priority benefit of Taiwan application serial no. 88115320, filed Sep. 6, 1999.
1. Field of Invention
The present invention relates to a power management control circuit for a computer system. More particularly, the present invention relates to a power management control circuit for implementing a suspend-to-RAM mode of operation in a microprocessor-based personal computer or workstation.
2. Description of Related Art
Ever since the introduction of an ATX specification for the main board of a personal computer by Intel Corporation of America, a power supplier is no longer a passively controlled mechanical switch just for providing power to a computer system. Not long thereafter, Intel, Microsoft and Toshiba together introduced an advanced configuration and power interface (ACPI) specification that particularly specifies four idling states representing the level of activity within a computer system. Depending on the amount of activities within a computer, energy can be saved by removing power from some devices. In the ACPI specification, the amount of activities from small to large is in the order of: State 1, stopping the CPU clock; state 2, suspending activities to RAM; state 3, suspending activities to disk; and, state 4, soft off. When the RAM is suspended, all other clock pulses except the real-time clock on the main circuit board are stopped temporarily. Under such circumstances, the CPU and other electric circuits stop working due to the absence of input clock pulses.
Many different types of memories are available in the market for use inside a computer system. Examples are fast page (FP) memory, extended data out (EDO) memory, and synchrotron dynamic random access memory (SDRAM). In general, each type of memory has its own particular characteristics. Hence, when system manufacturers design the suspend-to-RAM (STR) circuit, the manufacturers have to consider the characteristics of the particular type of memory used inside the computer. For example, if EDO memory is used, the north bridge circuit of a chipset still has to be powered up in the STR mode because all EDO memories need refreshing. In contrast, since SDRAM has self-refreshing properties, there is no need to supply power to the north bridge when the STR mode is activated. FIG. 1 is a timing diagram showing the signals on various control lines of SDRAM. As shown in FIG. 1, when a clock-enable CKE pin of an SDRAM is pulled down to a low voltage level, the SDRAM is in a self-refreshing mode. On the other hand, when the CKE pin is pulled up to a high voltage level, the SDRAM returns back from the self-refreshing mode. Due to the versatility of the SDRAM, EDO memory is gradually replaced in newer generation of computers. Therefore, method of implementing the energy-saving STR mode utilizing the special properties of SDRAM can be introduced.
Accordingly, the purpose of the present invention is to provide a system for implementing an energy-saving suspend-to-RAM (STR) mode of operation such that power to a north bridge circuit can be completely cut when the STR mode is activated.
A second purpose of the invention is to provide a system for implementing an energy-saving STR mode of operation such that data related to the system memory stored within the north bridge is temporarily transferred somewhere else. Hence, data can be returned to the north bridge immediately after the STR mode is over, and the re-establishment of system memory parameters from scratch can be avoided.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides an installation capable of implementing the energy-saving STR mode of operation in a computer system. The installation includes a first control chip (for example, a north bridge) having a register therein for storing system memory data; a second control chip (for example, a south bridge) coupled to the first control chip, wherein the second control chip acts according to the signal coming from a basic input/output system (BIOS) for stopping the power to the first control chip; a voltage converter coupled to the second control chip and the clock pulse pin of a system memory, wherein the voltage converter is used for pulling down the potential at the clock-enable pin of the system memory; and a memory unit coupled to the second control chip for temporarily storing data inside the register. When the STR mode is activated by the computer system, data inside the register is transferred to the memory unit. Voltage level at the clock-enable pin of the system memory is next pulled down by the second control chip. Lastly, power to the first control chip is cut off when signaled to do so by the BIOS, and so the computer system is switched into the STR mode of operation.
Although potential at the clock-enable pin is pulled down by the second control chip in the aforementioned illustration, the potential can also be designed to be pulled down by the first control chip, instead. In addition, the memory unit can be implemented using CMOS RAM or EEPROM within the second control chip or alternatively by using an external EEPROM connected by a bus.
The invention also provides a method of implementing an energy-saving STR mode of operation in a computer system. The computer system includes a central processing unit (CPU), a first control chip (north bridge) coupled to the CPU, a second control chip (south bridge), and a system memory. The first control chip and the second control chips are respectively coupled to a bus. The system memory is coupled to the first control chip. The first step in implementing STR mode of operation is for the computer system to decide whether the system needs to switch into a STR mode or needs to return from a STR mode. If the system needs to enter a STR mode, data stored in the register of the first control chip are transferred to a memory unit via the second control chip. Voltage level at a clock-enable pin of the system memory is next pulled down. The second control chip then cuts off power to the first control chip according to a signal returned from the BIOS, and so the computer system runs in the STR mode. On the other hand, if the computer system is already in the STR mode and needs to return to a normal mode, the second control chip returns power to the first control chip on being signaled by the BIOS. Voltage level at the clock-enable pin of the system memory is pulled up. The second control chip controls the transmission of data from the memory unit back to the register, thereby returning the computer system to the normal mode of operation.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.